--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:37:02 04/22/2012
-- Design Name:   
-- Module Name:   C:/Users/ulab/Desktop/compe-bricks/hardware/compe-bricks/nes_controller_tb.vhd
-- Project Name:  compe-bricks
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: nes_controller
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
use work.game_support.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY nes_controller_tb IS
END nes_controller_tb;
 
ARCHITECTURE behavior OF nes_controller_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT nes_controller
    PORT(
         clk : IN  std_logic;
         load : OUT  std_logic;
         serial_data : IN  std_logic;
			direction : out paddle_direction
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal serial_data : std_logic := '1';

 	--Outputs
   signal load : std_logic;
	signal direction : paddle_direction;

   -- Clock period definitions
   constant clk_period : time := 1 ms;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: nes_controller PORT MAP (
          clk => clk,
          load => load,
          serial_data => serial_data,
			 direction => direction
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin	      wait;
   end process;

END;
